1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a capacitive element and a method for the manufacture thereof.
2. Description of Related Art
The constitution of 1T-1C (single-transistor/single-capacitor) ferroelectric memory (FeRAM) is disclosed in "IEDM Digest of Technical Papers, 1997, pp. 613-616". In this example, a cell size of 12.5 .mu.m.sup.2 is achieved with a 0.5 .mu.m rule. This ferroelectric capacitor has a multilayered structure of Pt/PZT/Pt/TiN. The TiN layer of the upper electrode is connected via local wiring formed of TiN material and a W plug to one end of the main current path of a MOS transistor. The other end of the main current path of the MOS transistor is connected to a bit line.
The Pt layer is not oxidized during the heat treatment in oxygen which is necessary when forming a ferroelectric capacitor. Therefore, the Pt layer is also used as a plate line.
The Pt layer must be relatively thick because the plate line must have low resistance. As a result, expensive Pt is used in a large quantity, and chip costs become high.